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acsl-6xx0 multi-channel and bi-directional, 15 mbd digital logic gate optocoupler data sheet description acsl-6xx0 are truly isolated, multi-channel and bi-direc- tional, high-speed optocouplers. integration of multiple optocouplers in monolithic form is achieved through patented process technology. these devices provide full duplex and bi-directional isolated data transfer and communication capability in compact surface mount packages. available in 15 mbd speed option and wide supply voltage range. these high channel density make them ideally suited to isolating data conversion devices, parallel buses and peripheral interfaces. they are available in 8-pin and 16Cpin narrow-body soic package and are speci?ed over the temperature range of -40c to +100c. features available in dual, triple and quad channel con?gura- tions bi-directional wide supply voltage range : 3.0v to 5.5v high-speed: 15 mbd typical, 10 mbd minimum 10 kv/s minimum common mode rejection (cmr) at vcm = 1000v lsttl/ttl compatible safety and regulatory approvals C 2500vrms for 1 min per ul1577 C csa component acceptance C iec/en/din en 60747-5-2 16 pin narrow-body soic package for triple and quad channel -40 to 100c temperature range applications serial peripheral interface (spi) inter-integrated interface (i2c) full duplex communication isolated line receiver microprocessor system interfaces digital isolation for a/d and d/a conversion instrument input/output isolation ground loop elimination caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation, which may be induced by esd. lead (pb) free rohs 6 fully compliant r o hs 6 f u lly co m p l iant option s a v ai l a bl e ; - xxxe denote s a l ead- f ree product
2 device selection guide device number channel con?guration package acsl-6210 dual, bi-directional` 8-pin small outline acsl-6300 triple, all-in-one 16-pin small outline acsl-6310 triple, bi-directional, 2/1 16-pin small outline acsl-6400 quad, all-in-one 16-pin small outline acsl-6410 quad, bi-directional, 3/1 16-pin small outline acsl-6420 quad, bi-directional, 2/2 16-pin small outline pin description symbol description symbol description v dd1 power supply 1 gnd 1 power supply ground 1 v dd2 power supply 2 gnd 2 power supply ground 2 anode x led anode nc not connected cathode x led cathode v ox output signal truth table (positive logic) led output on l off h ordering information acsl-6xx0 is ul recognized with 2500 v rms for 1 minute per ul1577 and is approved under csa component accep- tance notice #5, file ca 88324. part number rohs compliant [1] package surface mount tape & reel iec/en/din en 60747-5-2 quantity acsl-6210 -00re so-8 x 100 per tube -06re so-8 x x 100 per tube -50re so-8 x x 1500 per reel -56re so-8 x x x 1500 per reel acsl-6300 acsl-6310 acsl-6400 acsl-6410 acsl-6420 -00te so-16 x 50 per tube -06te so-16 x x 50 per tube -50te so-16 x x 1000 per reel -56te so-16 x x x 1000 per reel note 1: the acsl-6xx0 product family is only o?ered in rohs compliant option. to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: acsl-6210-56re refers to ordering a surface mount so-8 package in tape and reel packaging with iec/en/din en 60747-5-2 safety approval in rohs compliant. example 2: acsl-6400-00te refers to ordering a surface mount so-16 package product in tube packaging and in rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information.
3 functional diagrams acsl-6210 - dual-ch, bi-dir acsl-6300 - triple-ch, all-in-one acsl-6310 - triple-ch, bi-dir (2/1) acsl-6400 - quad-ch, all-in-one acsl-6410 - quad-ch, bi-dir (3/1) acsl-6420 - quad-ch, bi-dir (2/2)
4 schematic diagrams acsl-6210 - dual-ch, bi-dir acsl-6300 - triple-ch, all-in-one acsl-6310 - triple-ch, bi-dir (2/1) shield gnd2 cathode1 4 5 6 7 vdd2 anode2 vo2 shield 1 2 anode1 3 8 gnd1 cathode2 vdd1 vo1 16 shield 1 2 15 14 anode1 cathode1 vd d gn d vo1 shield 3 4 13 cathode2 anode2 vo2 shield 5 6 12 10 9 cathode3 anode3 vd d gn d vo3 shield 1 3 anode3 4 14 gnd1 vdd1 vo3 cathode 3 13 shield 5 6 12 11 anode1 cathode1 vdd2 vo1 shield 7 8 10 9 cathode2 anode2 gnd2 vo2 the acsl-6xx0 series optocouplers feature the gaasp leds with proprietary back emission design. they o?er the designer a broad range of input drive current, from 7 ma to 15 ma, thus providing greater flexibility in designing the drive circuit. the output detector integrated circuit (ic) in the opto- coupler consists of a photodiode at the input of a two- stage ampli?er that provides both high gain and high bandwidth. the secondary ampli?er stage of the detector ic feeds into an open collector schottky-clamped transis- tor. the entire output circuit is electrically shielded so that any common-mode transient capacitively coupled from the led side of the optocoupler is diverted from the photodiode to ground. with this electric shield, the optocoupler can withstand transients that slopes up to 10,000v/s, and am- plitudes up to 1,000v.
5 acsl-6410 - quad-ch, bi-dir (3/1) acsl-6420 - quad-ch, bi-dir (2/2) schematic diagrams, continued shield 2 1 gnd1 vo4 shield 4 3 vdd1 vo3 14 13 anode3 cathode3 16 15 anode4 cathode 4 shield 5 6 12 11 anode1 cathode1 vdd2 vo1 shield 7 8 10 9 cathode2 anode2 gnd2 vo2 shield 13 gnd2 vo1 shield 12 vo2 shield 11 10 9 vdd2 gnd2 vo3 4 anode1 6 5 anode2 cathode2 8 7 anode3 cathode3 14 shield 1 2 3 gnd1 cathode1 vdd1 vo4 anode4 15 cathode4 16 shield 1 2 16 15 14 anode1 cathode1 vdd gn d vo1 shield 3 4 13 cathode2 anode2 vo2 shield 5 6 12 cathode3 anode3 vo3 shield 7 8 11 10 9 cathode4 anode4 vdd gn d vo4 acsl-6400 - quad-ch, all-in-one
6 acsl-6210 small outline so-8 package acsl-6300, acsl-6310, acsl-6400, acsl-6410 and acsl-6420 small outline so-16 package package outline drawings 87 65 4 3 2 1 0 . 228 (5 . 80) 0 . 244 (6 . 20) 0 .1 8 9 (4 . 80) 0 .19 7 (5 . 00) 0 .1 50 (3 . 80) 0 .1 57 (4 . 00) 0 . 0 1 3 (0 . 33) 0 . 020 (0 . 5 1 ) 0 . 040 ( 1. 0 1 6) 0 . 060 ( 1. 524) 0 . 004 (0 .1 0) 0 . 0 1 0 (0 . 25) 0 . 054 ( 1. 37) 0 . 06 9 ( 1. 75) 0 . 0 1 6 (0 . 40) 0 . 050 ( 1. 27) 0 . 008 (0 .19 ) 0 . 0 1 0 (0 . 25) 0 . 0 1 0 (0 . 25) 0 . 020 (0 . 50) x 45 0 8 d i mens i ons: i nc h es (m i ll i me t ers) m i n ma x 1 8 0 . 228 (5 . 7 91 ) 0 . 244 (6 .19 7) 0 . 386 ( 9. 802) 0 . 3 9 4 ( 9.999 ) 0 .1 52 (3 . 86 1 ) 0 .1 57 (3 .9 88) 0 . 0 1 3 (0 . 330) 0 . 020 (0 . 508) 0 . 040 ( 1. 0 1 6) 0 . 060 ( 1. 524) 0 . 050 ( 1. 270) 0 . 060 ( 1. 524) 0 . 054 ( 1. 372) 0 . 068 ( 1. 727) 0 . 004 (0 .1 02) 0 . 0 1 0 (0 . 24 9 ) 0 . 0 1 6 (0 . 406) 0 . 050 ( 1. 270) 0 . 0 1 0 (0 . 245) 0 . 020 (0 . 508) 0 . 008 (0 .191 ) 0 . 0 1 0 (0 . 24 9 ) x 45 0 - 8 ty p . d i mens i ons: i nc h es (m i ll i me t ers) m i n ma x
7 solder re?ow temperature pro?le recommended pb-free ir pro?le note: non-halide ?ux should be used note: non-halide ?ux should be used 0 time (seconds) temperature ( c) 200 100 50 150 100 200 250 300 0 30 sec . 50 sec . 30 sec . 160 c 140 c 150 c peak temp . 245 c peak temp . 240 c peak temp . 230 c soldering time 200 c preheating time 150 c, 9 0 30 sec . 2 . 5 c 0 . 5 c/sec . 3 c + 1 c/C0 . 5 c tight t y pical loose room temperature preheating rate 3 c + 1 c/C0 . 5 c/sec . reflow heating rate 2 . 5 c 0 . 5 c/sec .
8 regulatory information insulation and safety related speci?cations parameter symbol value units conditions minimum external air gap l(i01) 4.9 mm measured from input terminals to output (clearance) terminals, shortest distance through air minimum externa l tracking l(i02) 4.5 mm measured from input terminals to output (creepage) terminals, shortest distance path through body minimum internal plastic gap 0.08 mm insulation thickness between emitter and (internal clearance) detector; also known as distance through insulation tracking resistance cti 175 volts din iec 112/vde0303 part 1 (comparative tracking index) isolation group iiia material group (din vde 0110, 1/89, table 1) iec/en/din en 60747-5-2 insulation related characteristics (option x 6 x only) description symbol acsl-6 xx 0- x 6 x units installation classi?cation per din vde 0110/1.89, table 1 for rated mains voltage 150v rms i-iv for rated mains voltage 300v rms i-iii climatic classi?cation 55/100/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 560 v peak input to output test voltage, method b * v pr 1050 v peak v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc input to output test voltage, method a * v pr 840 v peak v iorm x 1.5 = v pr, type and sample test, t m = 60 sec, partial discharge < 5 pc highest allowable overvoltage * v iotm 4000 v peak (transient overvoltage, t ini = 10 sec) safety limiting values (maximum values allowed in the event of a failure) case temperature t s 175 c input current i s,input 150 ma output power p s,output 600 mw insulation resistance at t s , v io = 500v r io 10 9 *refer to the front of the optocoupler section of the current catalog, under product safety regulations section, iec/en/din en 60747-5-2, for a detailed description. note: isolation characteristics are guaranteed only within the safet y maximum ratings, which must be ensured by protective circ uits in applica- tion. ts-case temperature,c output power-ps input power-lp 700 600 500 400 300 200 100 0 0 200 50 25 75 100 125 150 175 is (ma) ps (mw)
9 absolute maximum ratings parameter symbol min . max . units storage temperature t s -55 125 c operating temperature t a -40 100 c supply voltage (1 minute maximum) v dd1 , v dd2 7 v reverse input voltage (per channel) v r 5 v output voltage (per channel) v o 7 v average forward input current [1] (per channel) i f 15 ma output current (per channel) i o 50 ma input power dissipation [2] (per channel) p i 27 mw output power dissipation [2] (per channel) p o 65 mw recommended operating conditions parameter symbol min . max . units operating temperature t a -40 100 c input current, low level [3] i fl 0 250 a input current, high level [4] i fh 7 15 ma supply voltage v dd1 , v dd2 3.0 5.5 v fan out (at r l = 1k) n 5 ttl loads output pull-up resistor r l 330 4k notes: 1. peaking circuits may produce transient input currents up to 50 ma, 50 ns max. pulse width, provided average current does no t exceed its max. values. 2. derate total package power dissipation, pt linearly above +95c free-air temperature at a rate of 1.57mw/c for the so8 pac kage mounted on low conductivity board per jesd 51-3. derate total package power dissipation, pt linearly above +80c free-air temperature at a rate of 1.59 mw/c for the so16 package mounted on low conductivity board per jesd 51-3. pt= number of channels multiplied by (pi+po). 3. the o? condition can be guaranteed by ensuring that v fl 0.8v. 4. the initial switching threshold is 7 ma or less. it is recommended that minimum 8 ma be used for best performance and to pe rmit guardband for led degradation. 0 10 20 30 40 50 60 70 80 9 0 100 0 20 40 60 80 100 120 t a - ambient temperature - o c p t - total power dissipation per channel - mw so-16 package so-8 package
10 electrical speci?cations over recommended operating range (3.0v v dd1 3.6v, 3.0v v dd2 3.6v, t a = -40c to +100c) unless otherwise speci?ed. all typical speci?cations are at t a = +25c , v dd1 = v dd2 = +3.3v. parameter symbol min . typ . max . units test conditions input threshold current i th 2.7 7.0 ma i ol(sinking) =13 ma, v o = 0.6v high level output current i oh 4.7 100.0 a i f = 250 a, v o = 3.3v low level output voltage v ol 0.36 0.68 v i ol(sinking) = 13 ma, i f = 7ma high level supply current i ddh 3.2 5.0 ma i f = 0 ma (per channel) low level supply current i ddl 4.6 7.5 ma i f = 10 ma (per channel) input forward voltage v f 1.25 1.52 1.80 v i f = 10 ma, t a = 25c input reverse breakdown voltage bv r 5.0 v i r = 10 a input diode temperature coe?cient ?v f / ?t a -1.8 mv/c i f = 10 ma input capacitance c in 80 pf f = 1 mhz, v f = 0v switching speci?cations over recommended operating range (3.0v v dd1 3.6v, 3.0v v dd2 3.6v, i f = 8.0 ma, t a = -40c to +100c) unless otherwise speci?ed. all typical speci?cations are at t a = +25c , v dd1 = v dd2 = +3.3v. parameter symbol min . typ . max . units test conditions maximum data rate 10 15 mbd r l = 350, c l = 15 pf pulse width t pw 100 ns r l = 350, c l = 15 pf propagation delay time t plh 52 100 ns r l = 350, c l = 15 pf to logic high output level [5] propagation delay time t phl 44 100 ns r l = 350, c l = 15 pf to logic low output level [6] pulse width distortion |t phl C t plh | |pwd| 8 35 ns r l = 350, c l = 15 pf propagation delay skew [7] t psk 40 ns r l = 350, c l = 15 pf output rise time (10 C 90%) t r 35 ns r l = 350, c l = 15 pf output fall time (10 C 90%) t f 12 ns r l = 350, c l = 15 pf logic high common mode |cm h | 10 kv/s v cm = 1000v, i f = 0 ma, transient immunity [8] v o = 2.0v, r l = 350, t a = 25c logic low common mode |cm l | 10 kv/s v cm = 1000v, i f = 8 ma, transient immunity [8] v o = 0.8v, r l = 350, t a = 25c notes: 5. t plh is measured from the 4.0 ma level on the falling edge of the input pulse to the 1.5v level on the rising edge of the output pul se. 6. t phl is measured from the 4.0 ma level on the rising edge of the input pulse to the 1.5v level on the falling edge of the output pul se. 7. t psk is equal to the worst case di?erence in t phl and/or t plh that will be seen between units at any given temperature and speci?ed test condi- tions. 8. cm h is the maximum common mode voltage slew rate that can be sustained while maintaining v o > 2.0v. cm l is the maximum common mode voltage slew rate that can be sustained while maintaining v o < 0.8v. the common mode voltage slew rates apply to both rising and falling common mode voltage edges.
11 electrical speci?cations over recommended operating range (4.5v v dd1 5.5v, 4.5v v dd2 5.5v, t a = -40c to +100c) unless otherwise speci?ed. all typical speci?cations are at t a = +25c, v dd1 = v dd2 = +5.0v. parameter symbol min . typ . max . units test conditions input threshold current i th 2.7 7.0 ma i ol(sinking) =13 ma, v o = 0.6v high level output current i oh 3.8 100.0 a i f = 250 a, v o = 5.5v low level output voltage v ol 0.36 0.6 v i ol(sinking) =13 ma, i f =7 ma high level supply current i ddh 4.3 7.5 ma i f = 0 ma (per channel) low level supply current i ddl 5.8 10.5 ma i f = 10 ma (per channel) input forward voltage v f 1.25 1.52 1.8 v i f = 10 ma, t a = 25c input reverse breakdown voltage bv r 5.0 v i r = 10 a input diode temperature coe?cient ?v f / ?t a -1.8 mv/c i f = 10 ma input capacitance c in 80 pf f = 1 mhz, v f = 0v switching speci?cations over recommended operating range (4.5v v dd1 5.5v, 4.5v v dd2 5.5v, i f = 8.0 ma, t a = -40c to +100c) unless otherwise speci?ed. all typical speci?cations are at t a =+25c, v dd1 = v dd2 = +5.0v. parameter symbol min . typ . max . units test conditions maximum data rate 10 15 mbd r l = 350, c l =15 pf pulse width t pw 100 ns r l = 350, c l =15 pf propagation delay time t plh 46 100 ns r l = 350, c l =15 pf to logic high output level [5] propagation delay time t phl 43 100 ns r l = 350, c l =15 pf to logic low output level [6] pulse width distortion |t phl C t plh | |pwd| 5 35 ns r l = 350, c l =15 pf propagation delay skew [7] t psk 40 ns r l = 350, c l =15 pf output rise time (10 C 90%) t r 30 ns r l = 350, c l =15 pf output fall time (10 C 90%) t f 12 ns r l = 350, c l =15 pf logic high common mode |cm h | 10 kv/s v cm = 1000v, i f =0 ma, transient immunity [8] v o = 2.0v, r l =350, t a = 25c logic low common mode |cm l | 10 kv/s v cm = 1000v, i f = 8 ma, transient immunity [8] v o = 0.8v, r l = 350, t a = 25c notes: 5. t plh is measured from the 4.0 ma level on the falling edge of the input pulse to the 1.5v level on the rising edge of the output pul se. 6. t phl is measured from the 4.0 ma level on the rising edge of the input pulse to the 1.5v level on the falling edge of the output pul se. 7. t psk is equal to the worst case di?erence in t phl and/or t plh that will be seen between units at any given temperature and speci?ed test condi- tions. 8. cm h is the maximum common mode voltage slew rate that can be sustained while maintaining v o > 2.0v. cm l is the maximum common mode voltage slew rate that can be sustained while maintaining v o < 0.8v. the common mode voltage slew rates apply to both rising and falling common mode voltage edges.
12 package characteristics all speci?cations are at t a =+25c. parameter symbol min . typ . max . units test conditions input-output momentary so8 v iso 2500 v rms rh 50%, t = 1 min withstand voltage [9] so16 v iso 2500 rh50%, t = 1 min input-output insulation [10] [11] so8 i i-o 5 a 45% rh, t=5 sec, v i-o = 3kv dc so16 i i-o 5 45% rh, t=5 sec, v i-o =3kv dc input-output resistance [10] so8 r i-o 10 9 10 11 v i-o = 500v dc so16 r i-o 10 9 10 11 v i-o = 500v dc input-output capacitance [10] so8 c i-o 0.7 pf f = 1 mhz so16 c i-o 0.7 f = 1 mhz input-input insulation so8 i i-i 0.005 a rh 45%, t=5 sec, v i-i =500v leakage current [12] so16 i i-i 0.005 rh45%, t=5 sec, v i-i =500v input-input resistance [12] so8 r i-i 10 11 rh45%, t= 5 sec, v i-i =500v so16 r i-i 10 11 rh45%, t=5 sec, v i-i =500v input-input capacitance [12] so8 c i-i 0.1 pf f = 1 mhz so16 c i-i 0.12 f = 1 mhz electrostatic discharge sensitivity this product has been tested for electrostatic sensitivity to the limits stated in the speci?cations. however, avago recommends that all integrated circuits be handled with appropriate care to avoid damage. damage caused by inappropriate handling or storage could range from per- formance degradation to complete failure. notes: 9. v iso is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for continuous vol tage rating, refer to the iec/en/din en 60747-5-2 insulation characteristics table (if applicable), the equipment level safety speci?cation or avago applica- tion note 1074 entitled optocoupler input-output endurance voltage. 10. measured between each input pair shorted together and all output connections for that channel shorted together. 11. in accordance to ul1577, each optocoupler is proof tested by applying an insulation test voltage 3000 vrms for 1 sec (lea kage detection current limit, i i-o 5 a). this test is performed before the 100% production test for partial discharge (method b) shown in the iec/en/din en 60747-5-2 insulation characteristics table, if applicable. 12. measured between inputs with the led anode and cathode shorted together.
13 typical performance 0 1 2 3 4 5 6 -60 -40 -20 0 20 40 60 80 100 120 t a - temperature - c i th - input threshold current - ma v dd = 3.3v v o = 0.6v r l = 350 r l = 1 k r l = 4 k figure 1. typical input threshold current vs. temperature for 3.3v operation. 0 1 2 3 4 5 6 -60 -40 -20 0 20 40 60 80 100 120 t a - temperature - c i th - input threshold current - ma v dd = 5.0v v o = 0.6v r l = 350 r l = 1 k r l = 4 k figure 2. typical input threshold current vs. temperature for 5v operation. 20 30 40 50 60 70 -60 -40 -20 0 20 40 60 80 100 120 t a - temperature - c i ol - low level output current - ma v dd = 3.3v v ol = 0.6v i f = 7.0 ma figure 3. typical low level output current vs. temperature for 3.3v operation. 20 30 40 50 60 70 -60 -40 -20 0 20 40 60 80 100 120 t a - temperature - c i ol - low level output current - ma v dd = 5.0v v ol = 0.6v i f = 7.0 ma i f = 10 ma figure 4. typical low level output current vs. temperature for 5v operation. figure 5. typical high level output current vs. temperature for 3.3v operation. 0 5 10 15 -60 -40 -20 0 20 40 60 80 100 120 t a - temperature - c i oh - high level output current - a v o = 3.3v i f = 250 a v dd = 3.3v 0 5 10 15 -60 -40 -20 0 20 40 60 80 100 120 t a - temperature - c i oh - high level ou tput current - a figure 6. typical high level output current vs. temperature for 5v operation. v dd = 5.0v v o = 5.0v i f = 250 a 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -60 -40 -20 0 20 40 60 80 100 120 t a - temperature - c v ol - low level output voltage - v i o = 13 m a figure 7. typical low level output voltage vs. temperature for 3.3v operation. v dd = 3.3v i f = 7 ma 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -60 -40 -20 0 20 40 60 80 100 120 t a - temperature - c v ol - low level output voltage - v i o = 13 m a figure 8. typical low level output voltage vs. temperature for 5v operation. v dd = 5.0v i f = 7 ma 0 1 2 3 4 5 6 7 8 9 10 -60 -40 -20 0 20 40 60 80 100 120 t a - temperature - c i dd - supply current per channel - ma i f = 10 ma i f = 0 ma figure 9. typical supply current per channel vs. temperature for 3.3v operation. v dd = 3.3v i ddl i ddh
14 typical performance, continued 0 1 2 3 4 5 6 7 8 9 10 -60 -40 -20 0 20 40 60 80 100 120 t a - temperature - c i dd - supply current per channel - ma figure 10. typical supply current per channel vs. temperature for 5v operation. i f = 10 ma i f = 0 ma v dd = 5.0v i ddl i ddh 0.001 0.01 0.1 1 10 100 1000 1.1 1.2 1.3 1.4 1.5 1.6 v f - forward voltage - v i f + v f C figure 11. typical input diode forward characteristics. t a = 25 c i f - forward current - ma 0 30 60 90 120 150 -60 -40 -20 0 20 40 60 80 100 120 t a - temperature - c figure 13. typical propagation delay vs. temperature for 5v operation. t plh , r l = 350 t phl , r l = 350 v dd = 5.0v i f = 8.0 ma t p - propagation delay - ns 0 10 20 30 40 -60 -40 -20 0 20 40 60 80 100 120 t a - temperature - c figure 14. typical pulse width distortion vs. temperature for 3.3v operation. r l = 350 v dd = 3.3v i f = 8.0 ma pwd - pulse width distortion - ns 0 10 20 30 40 -60 -40 -20 0 20 40 60 80 100 120 t a - temperature - c figure 15. typical pulse width distortion vs. temperature for 5v operation. r l = 350 v dd = 5.0v i f = 8.0 ma pwd - pulse width distortion - ns 0 30 60 90 120 150 -60 -40 -20 0 20 40 60 80 100 120 t a - temperature - c figure 12. typical propagation delay vs. temperature for 3.3v operation. t plh , r l = 350 t phl , r l = 350 t p - propagation delay - ns v dd = 3.3v i f = 8.0 ma
15 test circuits figure 16 . test circuit for t phl . t plh , t f, and t r . 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 pulse gen. zo = 50 tf = tr = 5ns input monitoring node i f c l * r l 0.1 f bypass *c l is approximately 15 pf which includes probe and stray wiring capacitance 3.3v or 5v acsl-6210 t phl t plh input i f output v o 1.5v i f = 4.0 ma i f = 8.0 ma 10% 10% 90% 90% output vo monitoring node t f t r output vo monitoring node r l 0.1 f bypass 3.3v or 5v acsl-6400 i f 1 8 9 16 1 8 9 16 pulse gen. zo = 50 v ff a b + _ vcm vo vo cm h switch at position "a": i f = 0 ma vo (min.) cm l vo (max.) vcm (peak) switch at position "b": i f = 8 ma 0 v 5 v 0.5 v figure 17 . test circuit for common mode transient immunity and typical waveforms .
16 application information on and off conditions the acsl-6xx0 series has the on condition de?ned by current, and the off condition de?ned by voltage. in order to guarantee that the optocoupler is off, the forward voltage across the led must be less than or equal to 0.8 volt for the entire opera ting temperature range. this has direct implications for the input drive circuit. if the design uses a ttl gate to drive the input led, then one has to ensure that the gate output voltage is su?cient to cause the forward voltage to be less than 0.8 volt. the typical threshold current for the acsl-6xx0 series optocouplers is 2.7 ma; however, this threshold could increase over time due to the aging e?ects of the led. drive circuit arrange- ments must provide for the on state led forward current of at least 7 ma, or more if faster operation is desired. maximum input current and reverse voltage the average forward input current should not exceed the 15 ma absolute maximum rating as stated; however, peaking circuits with transient input currents up to 50 ma are allowed provided the average current does not exceed 15 ma. if the input current maximum rating is exceeded, the local temperature of the led can rise, which in turn may a?ect the long-term reliability of the device. when designing the input circuit, one must also ensure that the input reverse voltage does not exceed 5 v. if the optocoupler is subjected to reverse voltage transients or accidental situations that may cause a reverse voltage to be applied, thus an anti- parallel diode across the led is recommended. suggested input circuits for driving the led figures 18, 19, and 20 show some of the several techniques for driving the acsl-6xx0 led. figure 18 shows the rec- ommended circuit when using any type of ttl gate. the bu?er pnp transistor allows the circuit to be used with ttl or cmos gates that have low sinking current capabil- ity. one advantage of this circuit is that there is very little variation in power supply current due to the switching of the optocoupler led. this can be important in high-reso- lution analog-to-digital (a/d) systems where ground loop currents due to the switching of the leds can cause distor- tion in the a/d output. figure 18 . ttl interface circuit for the acsl-6xx0 .
17 with a cmos gate to drive the optocoupler, the circuit shown in figure 19 can be used. the diode in parallel to the current limiting resistor speeds the turn-o? of the optocoupler led. any hc or hct series cmos gate can be used in this circuit. for high common-mode rejection applications, the drive circuit shown in figure 20 is recommended. in this circuit, only an open-collector ttl, or an open drain cmos gate can be used. this circuit drives the optocoupler led with a 220 ohm current-limiting resistor to ensure that an i f of 7 ma is applied under worst case conditions and thus guarantee the 10,000 v/s optocoupler common mode rejection rating. the designer can obtain even higher common-mode rejection performance than 10,000 v/s by driving the led harder than 7 ma. phase relationship to input the output of the optocoupler is inverted when compared to the input. the input is de?ned to be logic high when the led is on. if there is a design that requires the optocoupler to behave as a non-inverting gate, then figure 20 . high cmr drive circuit for the acsl-6xx0 . figure 21 . high voltage switching with acsl-6xx0 . figure 22 . high voltage and high current switching with acsl-6xx0 . figure 1 9. cmos drive circuit for the acsl-6xx0 . the series input drive circuit shown in figure 19 can be used. this input drive circuit has an inverting function, and since the optocoupler also behaves as an inverter, the total circuit is non-inverting. the shunt drive circuits shown in figures 18 and 20 will cause the optocoupler to function as an inverter. current and voltage limitations the absolute maximum voltage allowable at the output supply voltage pin and the output voltage pin of the opt- ocoupler is 7 volts. however, the recommended maximum voltage at these two pins is 5.5 volts. the output sinking current should not exceed 13 ma in order to make the low level output voltage be less than 0.6 volt. if the output voltage is not a consideration, then the absolute maximum current allowed through the acsl-6xx0 is 50 ma. if the output requires switching either higher currents or voltages, output bu?er stages as shown in figures 21 and 22 are suggested.
18 propagation delay, pulse-width distortion and propagation delay skew propagation delay is a ?gure of merit which describes how quickly a logic signal propagates through a system. the propaga- tion delay from low to high (t plh ) is the amount of time required for an input signal to propagate to the output,causing the output to change from low to high. similarly,the propagation delay from high to low (t phl ) is the amount of time required for the input signal to propagate to the output causing the output to change from high to low (see figure 16). pulse-width distortion (pwd) results when t plh and t phl di?er in value. pwd is de?ned as the di?erence between t plh and t phl and often determines the maximum data rate capability of a transmission system. pwd can be expressed in percent by dividing the pwd (in ns) by the minimum pulse width (in ns) being transmitted. typically, pwd on the order of 20-30% of the minimum pulse width is tolerable; the exact ?gure depends on the particular application (rs232, rs422, t-l, etc.). propagation delay skew,t psk , is an important parameter to consider in parallel data applica- tions where synchro- nization of signals on parallel data lines is a concern. if the parallel data is being sent through a group of op- tocouplers, di?erences in propagation delays will cause the data to arrive at the outputs of the optocouplers at di?erent times. if this di?erence in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocou- plers. propagation delay skew is defined as the difference between the minimum and maximum propagation delays,either t plh or t phl , for any given group of optocou- plers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). as illustrated in figure 23, if the inputs of a group of optocouplers are switched either on or off at the same time, t psk is the di?erence between the shortest propagation delay,either t plh or tphl, and the longest propagation delay,either t plh or t phl . as mentioned earlier,t psk can determine the maximum parallel data transmission rate. figure 24 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through opto- couplers. the ?gure shows data and clock signals at the inputs and outputs of the optocouplers. to obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data;if only one edge were used, the clock signal would need to be twice as fast. propagation delay skew repre- sents the uncertainty of where an edge might be after being sent through an op- tocoupler. figure 24 shows that there will be uncertainty in both the data and the clock lines. it is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled,or some of the data outputs may start to change before the clock signal has arrived. from these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t psk . a cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. the t psk speci?ed optocouplers o?er the advantages of guaranteed speci?cations for propagation delays, pulse- width distortion and propagation delay skew over the recommended temperature, input current, and power supply ranges. figure 23 . propagation delay skew C t psk . figure 24 . parallel data transmission example .
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